1. Field of the Invention
The present invention relates to a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method for the same.
2. Discussion of the Related Art
A lateral double diffused metal oxide semiconductor (LDMOS) is a sort of majority carrier device and also a representative of lateral type power device having quick switching responsiveness and high input impedance.
FIG. 1 is a cross-sectional view showing the structure of a conventional LDMOS device. Referring to the drawing, a semiconductor substrate 100 is divided by a device isolation layer 105 into a low voltage MOS (LV MOS) region A disposed on the left, and a high voltage MOS (HV MOS) region B disposed on the right.
The LV MOS region A and the HV MOS region B include gate electrodes 115 and 125, gate dielectric layers 135 and 200, source regions 145 and 180, source electrodes 155 and 185, drain regions 150 and 190, drain electrodes 160 and 195, spacers 120 and 130, P-type well regions 140 and 165. The HV MOS region B further includes an N-type well region 170. In addition, the HV MOS region B includes a P-type body 175 formed in the P-type well region 165, and a device isolation layer for drain extension 110.
Generally, in case of an HV MOS region over 30V, the drain extension device isolation layer 110 is formed between the gate electrode 125 and the drain region 190 in order to prevent concentration of electric fields on the edge of the gate electrode 125. The drain extension device isolation layer 110 may be a local oxidation of silicon (LOCOS) layer. In case of a submicron HV MOS, the drain extension device isolation layer 110 may have a shallow trench isolation (STI) structure.
Here, the drain extension device isolation layer 110 may be a part of the gate dielectric layer 200 extended to elongate a channel for a high-voltage current. A current generated from the source region 180 flows to the drain region 190 passing through, along or in the silicon adjacent to a surface of the drain extension device isolation layer 110.
Although the above-structured device isolation layer may improve a breakdown voltage, on the other hand, an on-resistance Ron is increased. Accordingly, the current drive capability may be less than optimal.
Especially, when the device isolation layer 110 has the STI structure, a border part adjoining the gate dielectric layer 200 is susceptible to a high-voltage current. Therefore, when electric fields are concentrated, a surface breakdown may be incurred. Accordingly, it becomes important to design the power device to have a minimal on-resistance while maintaining the breakdown voltage, which is in a trade-off relationship with the on-resistance.